1. Field of the Invention
The present invention relates to the field of integrated circuit design and more particularly to a method and device for implementing an application specific integrated circuit (ASIC) through the use of an iterative process in which increasingly greater percentages of the ASIC are implemented in one or more interim devices prior to the completion of the design.
2. Description of the Relevant Art
Integrated circuits have widespread applications in electronic systems of every variety. An integrated circuit is comprised of thousands of transistors fabricated on a monolithic crystalline lattice typically comprised of silicon or other semiconductor material. These plurality of transistors are selectively interconnected through the use of one or more interconnect layers comprised of conductive material to achieve a particular functionality, typically dictated by the application to which the integrated circuit is directed.
For some well-known applications such as the more popular microprocessors and memory devices, a single device is suitable for a large number of applications and a large number of customers. Examples of such so-called commodity integrated circuits includes, among others, .times.86 microprocessors and memory devices such as dynamic RAM (DRAM) and static RAM (SRAM) devices. Because commodity products can be sold in large quantities to a large number of customers, dedicated mask sets are typically employed in the fabrication of these devices. The relatively large one time or non-recurring engineering costs associated with the design and layout of a complex set of photomasks suitable for fabricating these commodity devices is typically justified by the extremely large number of units over which these non-recurring costs can be spread. In contrast to the commodity products, application specific or customer specific integrated circuits refer to, as their names imply, devices which are customized for the needs of a particular application or a particular customer. Application or customer specific integrated circuits are typically limited in the number of customers or the quantity in which the devices will be sold. Because of the inherently limited markets associated with customer or application specific integrated circuits, non-recurring engineering costs have a more dramatic impact on the per-unit cost of these types of integrated circuits. To combat these relatively higher non-recurring costs associated with customer and application specific integrated circuits (collectively referred to throughout the remainder of this application as ASICs), programmable devices of many varieties have been used for a number of years. In a typical programmable device, a common mask set is used to produce a standardized integrated circuit which can be customized either in the field or at a late stage in the semiconductor fabrication process. By utilizing a common set of photomasks and processing steps, the per-unit cost of programmable integrated circuits is minimized. Programmable integrated circuits, however, are typically unable to maximize the performance and minimize the surface area required to produce a particular integrated circuit function. The sacrifice in performance and increase in surface area (and therefore, per-unit cost) is typically justified for ASICs when the lifetime or total volume of sales expected for a given ASIC is relatively low. In certain applications, however, customers require custom-built integrated circuits and can justify the non-recurring costs associated with the circuits by a large expected net sales volume. Typically, however, the large ASIC customer requires the custom-built circuit to be reduced from a conceptual or behavioral level description to an implemented circuit in silicon in a short period of time. Achieving an adequate turnaround time for the design and implementation of ASICs becomes increasingly harder as the ASIC technology evolves. Because ASIC manufacturing technology is now able to achieve millions of transistors on a single device, the task of designing a suitably complex circuit able to take advantage of this technology requires greater and greater engineering effort and cost. While electronic design automation (EDA) tools have aided in the ability of ASIC designers to reduce the time and cost associated with implementing complex circuits, the evolution or progress of EDA tools has generally failed to keep pace with the ASIC process technology. In other words, while fabrication and manufacturing improvements have enabled ASIC manufacturers to produce increasingly complex and smaller devices, the tools utilized to simplify the design task have not experienced a commensurate improvement. The net result is that ever-increasing pressures are placed on ASIC manufacturer to produce the complex circuits associated with the state-of-the-art devices in a suitable timeframe.
Referring to FIG. 1, a simplified block diagram of a conventional ASIC design flow is presented to understand the difficulty in fabricating complex ASICs in a short period of time. Initially, in the process represented in FIG. 1 by reference numeral 102, the behavior of the system in an abstract sense is defined. At this point in the process, the specific implementation of the system is left undefined and the interrelationships among the various circuit elements that will ultimately comprise the system are temporarily ignored in order to achieve a manageable model. At this stage in the process, the design of the ASIC may be entered with a schematic capture editor or other suitable EDA tool. The system designer then typically attempts to describe the behavioral model defined in process step 102 with a hardware description language (HDL) as shown with respect to reference numeral 104. A hardware description language is a highly specialized software language optimized for describing various elements and the interrelationships among the elements of an electronic system. Well-known hardware description languages include, among others, Verilog HDL and VHDL as will be familiar to those skilled in the field of integrated circuit design. After the integrated circuit has been suitably captured in HDL format, a behavioral synthesis tool is typically employed to produce an RTL representation of the ASIC. An RTL description of an integrated circuit represents a lower level of abstraction than the behavioral model without incorporating all of the individual electronic elements that will ultimately comprise the ASIC. An RTL description of an integrated circuit describes the circuit in terms of a plurality of digital registers, clocking circuits, and logic elements that are combined to implement the desired function of the integrated circuit. From the RTL description derived in process step 106, a gate level description of the device is achieved through a gate level synthesis as shown in process step 108. At the gate level, the circuit is described in greater detail than in the RTL description using a combination of common logic gates and circuits such as AND gates, OR gates, XOR gates, counters, adders, and other common logic gates. After a gate level description of the device has been achieved, suitable EDA tools can be employed to produce a netlist consisting of the list of circuit elements required to produce the ASIC and the interconnections among the various elements. From this netlist, suitable place and route programs can be implemented to implement the circuit in an actual physical design that can be achieved with the process technology chosen for the fabrication of the circuit. After the physical design of the device has been produced, a mask set may be generated and the device fabricated. Suitable testing of the device may then begin to verify that the given circuit performs adequately. The simplified flow shown with respect to FIG. 1 is not meant to be representative of every stage of ASIC development but is rather intended to demonstrate the serial nature of the process. It should be further noted that, at each step represented in FIG. 1, various iterations of the process step are typically undertaken to optimize the performance of the circuit. In addition, a variety of simulation tools are available to simulate the circuit at the various levels of abstraction depicted with respect to FIG. 1.
It will be readily appreciated that the design process depicted in FIG. 1 is a serial process in which each successive step is undertaken only after the preceding step is ultimately completed. The serial nature of the conventional ASIC design flow was typically not thought to be problematic at a time when ASIC designs usually involved less than 100,000 transistors. As the circuit density and complexity of ASIC devices has steadily increased, however, it has become increasingly difficult and time consuming to complete each successive step required in the process. For example, in the time when typical ASICs incorporated less than approximately 100,000 transistors, the layout process represented in FIG. 1 by reference numeral 112 in which the circuit elements are given a physical dimension and location within the integrated circuit, was relatively routine. In addition, the time required to verify the behavior of the system using conventional simulation tools at the system definition level required an acceptably low number of iterations and could typically be accomplished within a time frame suitable for getting the device to market quickly. The problem, however, with the serial nature of the conventional ASIC design flow depicted in FIG. 1 is that the designer is unable to fully verify the device until the end of the design process at which time any mistakes in the design will require at least one or more iterations of the entire cycle. Moreover, as the complexity of ASIC devices has steadily increased, each of the designs steps described in the preceding paragraphs requires additional time and resources to complete. The increased time required to complete the appropriate design tasks associated with complex devices places enormous time pressure on system and logic designers to get their designs to market. It would be highly desirable to implement a method and associated circuitry that would enable designers to verify manageable portions of their designs at early stages of the design cycle.